The CHEST Center is funded by a combination of National Science Foundation grants and memberships by industry and non-profit institutions. CHEST coordinates university-based research with partner needs to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems.
CHEST areas of interest include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. More specifically, CHEST covers all levels of hardware and embedded systems design: system, architectural, board, microprocessor, embedded system, application specific integrated circuit (ASIC), field programmable gate array (FPGA), and other circuits. Threats to hardware and embedded devices cover a broad range of attack vectors with the integration of design, manufacturing, supply chains, operations, and complex assemblies of hardware, software, and firmware. Vulnerabilities can be introduced at any hardware design level and any stage of the product lifecycle. The NSF CHEST Center addresses security, assurance, and trust across all levels and stages. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
Hardware assurance, counterfeit detection, integrated circuit authentication, anti-reverse engineering and anti-tampering, secure communication protocols, formal verification, secure processor architectures, vulnerability analysis, infrastructure safety and resilience, and secure systems engineering.