The .gov means it’s official.
Federal government websites often end in .gov or .mil. Before
sharing sensitive information, make sure you’re on a federal government site.
The site is secure.
The https:// ensures that you are connecting to the official
website and that any information you provide is encrypted and transmitted securely.
Center Overview
The CHEST Center is funded by a combination of National Science Foundation grants and memberships by industry and non-profit institutions. CHEST coordinates university-based research with partner needs to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems.
CHEST areas of interest include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. More specifically, CHEST covers all levels of hardware and embedded systems design: system, architectural, board, microprocessor, embedded system, application specific integrated circuit (ASIC), field programmable gate array (FPGA), and other circuits. Threats to hardware and embedded devices cover a broad range of attack vectors with the integration of design, manufacturing, supply chains, operations, and complex assemblies of hardware, software, and firmware. Vulnerabilities can be introduced at any hardware design level and any stage of the product lifecycle. The NSF CHEST Center addresses security, assurance, and trust across all levels and stages. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
Universities
- University of Virginia
- University of Cincinnati
- University of Texas, Dallas
- University of California, Davis
- University of Connecticut
- Northeastern University
Center Personnel
Dr. Marty Emmert
CHEST Director, University of Cincinnati
+1 513 556 4358
john.emmert@uc.edu
Dr. Yiorgos Makris
CHEST Site Director, University of Texas at Dallas
+1 972 883 4360
yiorgos.makris@utdallas.edu
Dr. Houman Homayoun
CHEST Site Director, University of California Davis
+1 530 754 7700
hhomayoun@ucdavis.edu
Dr. John Chandy
CHEST Site Director, University of Connecticut
+1 860 486 3622
john.chandy@uconn.edu
Dr. Yunsi Fei
CHEST Site Director, Northeastern University
+1 617 373 3004
yfei@ece.neu.edu
Dr. Jim Lambert
CHEST Site Director, University of Virginia
+1 972 883 4360
jhl6d@virginia.edu
Research Focus
Embedded Systems Security and Trust including: hardware assurance, counterfeit detection, integrated circuit authentication, anti-reverse engineering and anti-tampering, secure communication protocols, formal verification, secure processor architectures, vulnerability analysis, infrastructure safety and resilience, and secure systems engineering.
Awards
The Center for Hardware and Embedded Systems Security and Trust (CHEST) coordinates university-based research with needs of industry and government partners to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems. Interests of CHEST include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. The CHEST Center addresses a range of attack vectors across design, operation, manufacturing, supply chains, and integration of the hardware, software, and firmware to a variety of systems. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the University of California Davis (UC Davis) will lead CHEST efforts for hardware and embedded system security and trust at the system, architecture and circuit levels. Topics include : (i) Application-specific integrated circuit (ASIC) design flow for security, digital logic reverse engineering, hardware trojan detection and prevention, (ii) Detecting and preventing malicious and side-channel attacks, preventing IoT malware epidemics, secure processor architecture to prevent side-channel attacks and (iii) Security at the system/application levels including secure deep learning and artificial intelligence, cryptography and secure web browser for embedded system and hardware based rootkit.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all CHEST projects that are led by UC Davis are permanently archived in digital format on the UC Davis file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UC Davis computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the University of California Davis (UC Davis) will lead CHEST efforts for hardware and embedded system security and trust at the system, architecture and circuit levels. Topics include : (i) Application-specific integrated circuit (ASIC) design flow for security, digital logic reverse engineering, hardware trojan detection and prevention, (ii) Detecting and preventing malicious and side-channel attacks, preventing IoT malware epidemics, secure processor architecture to prevent side-channel attacks and (iii) Security at the system/application levels including secure deep learning and artificial intelligence, cryptography and secure web browser for embedded system and hardware based rootkit.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all CHEST projects that are led by UC Davis are permanently archived in digital format on the UC Davis file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UC Davis computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The Center for Hardware and Embedded Systems Security and Trust (CHEST) coordinates university-based research with needs of industry and government partners to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems. Interests of CHEST include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. The CHEST Center addresses a range of attack vectors across design, operation, manufacturing, supply chains, and integration of the hardware, software, and firmware to a variety of systems. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design, operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the CHEST universities, the University of Virginia (UVA) leads in identifying testbeds for improving security and trust at the level of integrated systems. UVA develops methodology for systemic risk, resilience, reliability, logistics, data analytics, and systems engineering. Research topics include (i) resource allocation and priorities of large-scale systems; (ii) tracking emergent and future conditions of supply chains; and (iii) aggregating trust and security of devices to quantification of system resilience.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, provides the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all CHEST Center projects that are led by UVA are permanently archived in digital format on the UVA file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UVA computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design, operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the CHEST universities, the University of Virginia (UVA) leads in identifying testbeds for improving security and trust at the level of integrated systems. UVA develops methodology for systemic risk, resilience, reliability, logistics, data analytics, and systems engineering. Research topics include (i) resource allocation and priorities of large-scale systems; (ii) tracking emergent and future conditions of supply chains; and (iii) aggregating trust and security of devices to quantification of system resilience.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, provides the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all CHEST Center projects that are led by UVA are permanently archived in digital format on the UVA file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UVA computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The Center for Hardware and Embedded Systems Security and Trust (CHEST) coordinates university-based research with needs of industry and government partners to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems. Interests of CHEST include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. The CHEST Center addresses a range of attack vectors across design, operation, manufacturing, supply chains, and integration of the hardware, software, and firmware to a variety of systems. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits (ICs) and boards. Among the universities, The University of Texas at Dallas (UTD) will lead the research efforts for addressing hardware security and trust aspects of analog and Radio Frequency (RF) ICs and systems, as well as at the microprocessor architecture level. This will include research topics embodying (i) covert channel attack detection and mitigation in standards-compliant wireless networks, (ii) design obfuscation techniques to protect analog/RF ICs against counterfeiting and Intellectual Property (IP) piracy, (iii) transistor-level reconfigurable hardware solutions for design obfuscation, and (iv) statistical and machine learning-based methods for hardware Trojan detection, provenance attestation, and hardware-based workload execution forensics.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all projects led by UTD will be permanently archived in digital format on the UTD file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UTD computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits (ICs) and boards. Among the universities, The University of Texas at Dallas (UTD) will lead the research efforts for addressing hardware security and trust aspects of analog and Radio Frequency (RF) ICs and systems, as well as at the microprocessor architecture level. This will include research topics embodying (i) covert channel attack detection and mitigation in standards-compliant wireless networks, (ii) design obfuscation techniques to protect analog/RF ICs against counterfeiting and Intellectual Property (IP) piracy, (iii) transistor-level reconfigurable hardware solutions for design obfuscation, and (iv) statistical and machine learning-based methods for hardware Trojan detection, provenance attestation, and hardware-based workload execution forensics.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all projects led by UTD will be permanently archived in digital format on the UTD file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UTD computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The Center for Hardware and Embedded Systems Security and Trust (CHEST) coordinates university-based research with needs of industry and government partners to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems. Interests of CHEST include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. The CHEST Center addresses a range of attack vectors across design, operation, manufacturing, supply chains, and integration of the hardware, software, and firmware to a variety of systems. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the University of Cincinnati will lead CHEST efforts for hardware and embedded system security and trust at the circuit level. Topics include methods for designing, detecting, avoiding, mitigating, and protecting against malicious attacks: (i) side channel attack avoidance and mitigation; (ii) split manufacturing and additive components for HW integrity monitoring; and (iii) hardware acceleration for enhancing encryption/obfuscation, camouflaging, split manufacturing, Trojan detection, reverse engineering, and watermarking applications.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all projects led by the University of Cincinnati (UC) will be permanently archived in digital format on the UC file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UC computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the University of Cincinnati will lead CHEST efforts for hardware and embedded system security and trust at the circuit level. Topics include methods for designing, detecting, avoiding, mitigating, and protecting against malicious attacks: (i) side channel attack avoidance and mitigation; (ii) split manufacturing and additive components for HW integrity monitoring; and (iii) hardware acceleration for enhancing encryption/obfuscation, camouflaging, split manufacturing, Trojan detection, reverse engineering, and watermarking applications.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all projects led by the University of Cincinnati (UC) will be permanently archived in digital format on the UC file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UC computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The Center for Hardware and Embedded Systems Security and Trust (CHEST) coordinates university-based research with needs of industry and government partners to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems. Interests of CHEST include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. The CHEST Center addresses a range of attack vectors across design, operation, manufacturing, supply chains, and integration of the hardware, software, and firmware to a variety of systems. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the University of Connecticut will lead CHEST efforts for hardware and embedded system security and trust at the circuit and systems level. Research topics include (i) anti-tamper technologies that help prevent reverse engineering; (ii) counterfeit detection and prevention in the supply chain of integrated circuits and component subsystems, and (iii) methods to automatically configure hardware components in distributed embedded systems.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all projects led by the University of Connecticut (UConn) are permanently archived in digital format on the UConn file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UConn computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the University of Connecticut will lead CHEST efforts for hardware and embedded system security and trust at the circuit and systems level. Research topics include (i) anti-tamper technologies that help prevent reverse engineering; (ii) counterfeit detection and prevention in the supply chain of integrated circuits and component subsystems, and (iii) methods to automatically configure hardware components in distributed embedded systems.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all projects led by the University of Connecticut (UConn) are permanently archived in digital format on the UConn file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival UConn computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The Center for Hardware and Embedded Systems Security and Trust (CHEST) coordinates university-based research with needs of industry and government partners to advance knowledge of security, assurance, and trust for electronic hardware and embedded systems. Interests of CHEST include identification, detection, monitoring, mitigation, and elimination of vulnerabilities that affect hardware and embedded systems. The CHEST Center addresses a range of attack vectors across design, operation, manufacturing, supply chains, and integration of the hardware, software, and firmware to a variety of systems. The Center is inventing and disseminating technologies, practices, and guidelines to stakeholders and educating a next generation of experts.
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the Northeastern University (NU) leads CHEST efforts for designing, mitigating, and protecting hardware and embedded systems against malicious attacks at the levels of architecture and embedded devices. Topics include: (i) clean-slate secure architecture to balance performance and information security on CPUs and accelerators; (ii) lightweight hardware primitives for security at the edge of Internet-of-Things; and (iii) hardening techniques for deep learning systems on edge computing under adversarial attacks.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all CHEST projects that are led by NU are permanently archived in digital format on the NU file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival NU computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
The NSF CHEST Center addresses security, assurance, and trust across several levels: Large-scale systems, embedded systems, design and operations, requirements, standards, manufacturing, supply chains, and integrated circuits and boards. Among the universities, the Northeastern University (NU) leads CHEST efforts for designing, mitigating, and protecting hardware and embedded systems against malicious attacks at the levels of architecture and embedded devices. Topics include: (i) clean-slate secure architecture to balance performance and information security on CPUs and accelerators; (ii) lightweight hardware primitives for security at the edge of Internet-of-Things; and (iii) hardening techniques for deep learning systems on edge computing under adversarial attacks.
Security, assurance, and trust of integrated cyber-physical systems enable meeting fundamental human needs, along with supporting broader social, environmental, and economic progress of the nation. The ability of systems to absorb disruptive shocks and recover with minimal loss is key to protecting human lives and property. The NSF CHEST Center influences the practices of industry, government, and the military in design, protection, and resilience to vulnerabilities associated with hardware and embedded systems. Improving assurance and trust contributes to the reducing the frequencies and severities of adverse events with attention to system missions, performance, schedule, and cost.
The NSF CHEST Center website, www.nsfchest.org, is the repository for all publicly accessible data, code, results, etc. These pages will be maintained for at least as long as the CHEST Center is active. In addition, all CHEST projects that are led by NU are permanently archived in digital format on the NU file servers with sufficient provisions for backup and recovery in case of equipment failure. All archival NU computers and servers are backed up on a regular basis.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >
Member Organizations
IUCRC affiliated member organizations are displayed as submitted by the Center. Non-federal organizations are not selected, approved, or otherwise endorsed by the U.S. National Science Foundation.- Air Force Research Laboratory (AFRL)
- Air Force Life Cycle Management Center
- Analog Devices
- Army
- Booz Allen Hamilton
- Commonwealth Center for Advanced Logistics (CCALS)
- Department of Defense
- Draper Lab
- Edaptive Computing
- Fermata Energy
- Global Foundries
- MITRE
- National Air & Space Intelligence Center
- NAVSEA CRANE
- Northrup Grumman
- Raytheon
- Riverside Research
- Sandia National Laboratories
- Systems Planning and Analysis
The opinions, findings, and conclusions or recommendations expressed are those of the Center author(s) and do not necessarily reflect the views of the U.S. National Science Foundation.