The .gov means it’s official.
Federal government websites often end in .gov or .mil. Before sharing sensitive information, make sure you’re on a federal government site.

The site is secure.
The https:// ensures that you are connecting to the official website and that any information you provide is encrypted and transmitted securely.

Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP)

Center Overview

Microelectronic chips based on semiconductor technology have had a profound impact on human lives in areas such as energy, advanced manufacturing, public health, security, business, and artificial intelligence. However, their ever-increasing power consumption has not only become the bottleneck for performance improvement but has also led to the rapidly increasing carbon footprint of our expanding information infrastructure.

The goal of the Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP) is to create breakthrough integrated solutions, from materials and devices to circuits and architectures, that would lead to highly energy-efficient chips at advanced technology nodes for low-power digital and radio-frequency (RF) applications. The Center will make a sustained and meaningful impact on the next-generation computing infrastructure by partnering with industry leaders, as well as national and Department of Defense labs. Together with its industry members, ASAP will support the national semiconductor research agenda with fundamental research and grand challenges to build systems that have 100 times lower energy and higher performance compared to the most advanced solutions available today. The Center will focus on pre-competitive fundamental research and will engage in joint critical R&D projects with our industry members, leading to commercial technologies within the next decade.

ASAP will support the nation’s priorities in advancing modernization, fostering innovation, broadening participation, and preparing the future workforce. Current college curricula are designed to prepare experts in isolated levels and sectors of chip technology, which do not meet the requirements of the industry in the more-than-Moore era. With ASAP’s highly convergent research scope, students will receive training without traditional boundaries between disciplines of materials science, nanoscale electronic and photonic device fabrication and characterization, computational modeling, and circuit and architecture design. With their cross-disciplinary expertise, ASAP students will be ready to take on highly skilled tech jobs in existing and emerging industries, for example, in advanced chip design and manufacturing and nanotechnology. ASAP will also provide education and training to people from marginalized communities and help them find jobs in high-growth sectors.

Universities

University of Illinois, Urbana-Champaign

View Center Website

Center Personnel

Shaloo Rakheja
Center Director and Principal Investigator (PI)
+1 217 244 3616
rakheja@illinois.edu

Qing Cao
Associate Director
+1 217 300 8327
qingcao2@illinois.edu

Naresh Shanbhag
Co-PI
+1 217 244 0041
shanbhag@illinois.edu

Paul Braun
Co-PI
+1 217 244 7293
pbraun@illinois.edu

Mallory Gorman
Operations Manager

magorma2@illinois.edu

Irfan Ahmad
Innovation Director
+1 217 333 2015
isahmad@illinois.edu

Research Focus

The ASAP has three research themes as described below.

Theme 1: Materials Discovery for Next-Generation Electrical and Optical Interconnects. Energy consumption and delays associated with interconnects have become a crucial bottleneck for improving the performance of computer chips, especially for data-intensive applications. ASAP is developing innovative ideas to discover material options for future electronics beyond the copper interconnect and low-k dielectrics currently used in state-of-the-art microprocessors and classical optical waveguides. Specifically, ASAP will discover strategies to advance material designs, beginning with computational efforts and augmented by artificial intelligence (AI) methods, to provide fundamental insights. These will complement experimental efforts related to (i) new conductive materials with better scalability and reliability against electromigration compared to copper, (ii) new dielectrics with lower dielectric constant but higher mechanical robustness compared to porous organosilicate glass, and (iii) new optical interconnect materials and concepts with better scalability. The Center will also develop advanced tools and processes to deposit and pattern these new materials at the wafer-scale, and new metrology methods to characterize the material structures, properties, and reliability.

Theme 2: Heterogeneous Integration. Future challenges in power delivery and high connectivity may not be addressed by simply scaling down or finessing computing platforms using existing materials; rather, entirely new materials systems and phenomena will have to be exploited. Integration of photonics, electronics, spintronics, and mixed-signal circuits can yield multi-functional platforms with significantly higher integration density. This theme will focus on the development of hybrid computing platforms in which data movement is minimized by co-locating logic and memory, while also using unconventional materials as the channel and gate dielectrics for energy-efficient logic devices. New fundamental design rules that will enable the heterogeneous integration of disparate material structures and devices with distinct modalities will be identified. Creating novel fabrication pathways for monolithic integration of memory, sensing, and logic functionalities and complemented with novel characterization and multi-scale devices-to-systems modeling techniques are the main focus.

Theme 3: Circuits and Architectures for Highly Energy-Efficient Computing. Today’s AI workloads are based on deep neural networks and other machine learning algorithms, which are computationally complex and require the processing of large volumes of data. When implemented on von Neumann architectures, such as Graphics Processing Units, the resulting data movement dominates the latency and energy costs due to the existence of the so-called “memory wall.” To alleviate the drawbacks of existing computing systems, the ASAP Center will seek radically different circuit and architecture approaches, as well as cross-layer solutions, to increase the compute density and energy efficiency by >100 times compared to state-of-the-art approaches. Examples of new architecture approaches include in-memory computing, analog and brain-inspired computing, and stochastic computing platforms. Ideas that leverage the co-design approach, where investigations at different levels of the design hierarchy inform and guide each other to yield system-level solutions with maximum benefit, are being explored. Circuits and architectures based on heterogeneous materials and devices and those that utilize the emergent physics in non-silicon substrates are also being investigated.

Awards

2231625

IUCRC Phase I: University of Illinois at Urbana-Champaign (UIUC): Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP)

This Phase I award supports the Industry University Cooperative Research Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP) at the University of Illinois - Urbana-Champaign. Integrated circuits or “chips”, containing billions of transistors within the size of a fingernail, have had a profound impact on human lives, and enabled many fundamental scientific discoveries. However, in state-of-the-art microprocessors and associated computing machines, interconnects or wires that transport data between different components start to dominate the overall power consumption and performance, which has become a critical bottleneck for future semiconductor technologies. In alliance with industry members, the Center will develop breakthrough solutions that alleviate interconnect challenges and improve the energy efficiency of next-generation information-processing systems. The Center will address the critical national need for US technology supremacy in future microelectronics. In addition to technology development, the center will foster unique training opportunities for a diverse workforce with technical competence, socially responsible leadership, and entrepreneurship. The Center has a rich portfolio of outreach activities, including working with under-represented and low-income K-12 students, training students from two-year institutions of higher education (community colleges/technical colleges), and developing a women-in-microelectronics program. The Center will work closely with UIUC’s Institute for Inclusion, Diversity, Equity, and Access to recruit, educate, and retain diverse talents and empower them to become future leaders in US-based microelectronics and other related industries. The Center’s research is structured into three tightly integrated themes including materials discovery for electrical and optical interconnects, heterogeneous 3D integration, and highly energy-efficient circuits and architectures. The materials-to-architectures co-design approach will allow the Center to address the fundamental technological roadblocks toward enabling future microprocessors with higher performance but lower energy consumption. By integrating disparate components on silicon, such as interconnects based on quantum materials, nanodielectrics, magnetic and ferroelectric memory, nano-photonics, and III-V elements, the Center seeks to reduce the energy-delay cost of data communication hundred-fold in chips adopting novel processing-in-memory architectures. Center faculty members have cross-disciplinary expertise in materials science, nanoscale electronic and photonic device fabrication and characterization, computational modeling, and circuit and architecture design. By focusing on technologies that are mutually beneficial for digital and RF applications, the Center will collaboratively address the research needs of its industrial members representing different microelectronics sectors and thus different research priorities. The Center will engage with semiconductor foundries, chip manufacturers, small startups, DOE national labs, and DoD labs and collaboratively seek to make a sustained and meaningful impact on the next-generation information-processing systems. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. Read More >

Member Organizations

IUCRC affiliated member organizations are displayed as submitted by the Center. Non-federal organizations are not selected, approved, or otherwise endorsed by the U.S. National Science Foundation.

Advanced Micro Devices, Inc. (AMD)
Department of Defense
IBM
LG
Sandia National Laboratories
Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC)

The opinions, findings, and conclusions or recommendations expressed are those of the Center author(s) and do not necessarily reflect the views of the U.S. National Science Foundation.